This invention relates to packaging of semiconductors, and more particularly to small form factor semiconductor packages.
Semiconductor packages generally have allowed access to the internal die only from a bottom side of the package. This limitation creates an increase in the footprint or size of the package. Additionally, a large number of pins, such as input/output (I/O) and power/ground pins have to be replicated in numerous locations. In addition to these issues, many products are migrating to implementing systems with multiple integrated circuit die in a package. In the past, such circuits have been implemented both in a stacked configuration and a non-stacked configuration which clearly is not size efficient. For those packages with stacked integrated circuit die, the amount of scrap product created during an early manufacturing phase of a part the yield is typically low. It is desirable to be able to rework or modify an integrated circuit in a stacked die formation after encapsulation has occurred. This is not possible with most packages.
Because electronic products continue to be miniaturized, various integrated circuits are combined to form systems with only a few integrated circuits. Existing semiconductor packages are limiting with respect to what types of products may be combined and are limiting with respect to the package type that can be inter-coupled. U.S. Pat. No. 6,225,688 entitled xe2x80x9cStacked Microelectronic Assembly And Method Thereforxe2x80x9d proposes an assembly having a metal tape that is folded and terminates in a single I/O port. The tape is connected to only one side of each die and each die is accessible only from one side. The length through the tape from the I/O to the farthest die would create speed and noise problems for wireless applications. Also, folding of conductive tape may create conductivity reliability and is sensitive to mechanical stresses.